Timer Module (TIM16B8CV2) Block Description
14.3.2.14 Timer Input Capture/Output Compare Registers High and Low 0–7
(TCxH and TCxL)
Module Base + 0x0010 = TC0H
0x0012 = TC1H
0x0018 = TC4H
0x001A = TC5H
0x001C = TC6H
0x001E = TC7H
0x0014 = TC2H
0x0016 = TC3H
15
14
13
12
11
10
9
0
R
Bit 15
W
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Reset
0
0
0
0
0
0
0
0
Figure 14-22. Timer Input Capture/Output Compare Register x High (TCxH)
Module Base + 0x0011 = TC0L
0x0013 = TC1L
0x0019 = TC4L
0x001B = TC5L
0x001D = TC6L
0x001F = TC7L
0x0015 = TC2L
0x0017 = TC3L
7
6
5
4
3
2
1
0
R
Bit 7
W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
0
0
0
0
0
0
0
0
Figure 14-23. Timer Input Capture/Output Compare Register x Low (TCxL)
Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the
free-running counter when a defined transition is sensed by the corresponding input capture edge detector
or to trigger an output action for output compare.
Read: Anytime
Write: Anytime for output compare function.Writes to these registers have no meaning or effect during
input capture. All timer input capture/output compare registers are reset to 0x0000.
NOTE
Read/Write access in byte mode for high byte should takes place before low
byte otherwise it will give a different result.
S12P-Family Reference Manual, Rev. 1.13
490
Freescale Semiconductor
FREESCALE [ Freescale ]
