Timer Module (TIM16B8CV2) Block Description
Table 14-20. PAFLG Field Descriptions
Field
Description
1
Pulse Accumulator Overflow Flag — Set when the 16-bit pulse accumulator overflows from 0xFFFF to 0x0000.
PAOVF
Clearing this bit requires writing a one to this bit in the PAFLG register while TEN bit of TSCR1 or PAEN bit of
PACTL register is set to one.
0
PAIF
Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the IOC7 input pin.In event
mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at
the IOC7 input pin triggers PAIF.
Clearing this bit requires writing a one to this bit in the PAFLG register while TEN bit of TSCR1 or PAEN bit of
PACTL register is set to one. Any access to the PACNT register will clear all the flags in this register when TFFCA
bit in register TSCR(0x0006) is set.
14.3.2.17 Pulse Accumulators Count Registers (PACNT)
Module Base + 0x0022
15
14
13
12
11
10
9
0
R
W
PACNT15
PACNT14
PACNT13
PACNT12
PACNT11
PACNT10
PACNT9
PACNT8
Reset
0
0
0
0
0
0
0
0
Figure 14-26. Pulse Accumulator Count Register High (PACNTH)
Module Base + 0x0023
7
6
5
4
3
2
1
0
R
PACNT7
W
PACNT6
PACNT5
PACNT4
PACNT3
PACNT2
PACNT1
PACNT0
Reset
0
0
0
0
0
0
0
0
Figure 14-27. Pulse Accumulator Count Register Low (PACNTL)
Read: Anytime
Write: Anytime
These registers contain the number of active input edges on its input pin since the last reset.
When PACNT overflows from 0xFFFF to 0x0000, the Interrupt flag PAOVF in PAFLG (0x0021) is set.
Full count register access should take place in one clock cycle. A separate read/write for high byte and low
byte will give a different result than accessing them as a word.
NOTE
Reading the pulse accumulator counter registers immediately after an active
edge on the pulse accumulator input pin may miss the last count because the
input has to be synchronized with the bus clock first.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
493
FREESCALE [ Freescale ]
