Analog-to-Digital Converter (ADC12B10C)
Address
Name
Bit 7
6
5
4
3
2
1
Bit 0
R
W
R
See Section 9.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 9.3.2.12.2, “Right Justified Result Data (DJM=1)”
0x0020
ATDDR8
See Section 9.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 9.3.2.12.2, “Right Justified Result Data (DJM=1)”
0x0022
ATDDR9
W
R
Unimple-
mented
0
0
0
0
0
0
0
0
0x0024 -
0x002F
W
= Unimplemented or Reserved
Figure 9-2. ADC12B10C Register Summary (Sheet 3 of 3)
9.3.2
Register Descriptions
This section describes in address order all the ADC12B10C registers and their individual bits.
9.3.2.1
ATD Control Register 0 (ATDCTL0)
Writes to this register will abort current conversion sequence.
Module Base + 0x0000
7
6
5
4
3
2
1
0
R
W
0
0
0
Reserved
WRAP3
WRAP2
WRAP1
WRAP0
Reset
0
0
0
0
1
1
1
1
= Unimplemented or Reserved
Figure 9-3. ATD Control Register 0 (ATDCTL0)
Read: Anytime
Write: Anytime, in special modes always write 0 to Reserved Bit 7.
Table 9-1. ATDCTL0 Field Descriptions
Field
Description
3-0
Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing multi-
WRAP[3-0] channel conversions. The coding is summarized in Table 9-2.
Table 9-2. Multi-Channel Wrap Around Coding
Multiple Channel Conversions (MULT = 1)
WRAP3 WRAP2 WRAP1 WRAP0
Wraparound to AN0 after Converting
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Reserved(1)
AN1
AN2
AN3
AN4
AN5
S12P-Family Reference Manual, Rev. 1.13
310
Freescale Semiconductor
FREESCALE [ Freescale ]
