Analog-to-Digital Converter (ADC12B10C)
Table 9-3. ATDCTL1 Field Descriptions (continued)
Field
Description
4
Discharge Before Sampling Bit
SMP_DIS
0 No discharge before sampling.
1 The internal sample capacitor is discharged before sampling the channel. This adds 2 ATD clock cycles to
the sampling time. This can help to detect an open circuit instead of measuring the previous sampled
channel.
3–0
External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG3-0 inputs
ETRIGCH[3:0] as source for the external trigger. The coding is summarized in Table 9-5.
Table 9-4. A/D Resolution Coding
SRES1
SRES0
A/D Resolution
0
0
1
1
0
1
0
1
8-bit data
10-bit data
12-bit data
Reserved
Table 9-5. External Trigger Channel Select Coding
ETRIGSEL ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0
External trigger source is
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN9
AN9
AN9
AN9
AN9
AN9
ETRIG0(1)
ETRIG11
ETRIG21
ETRIG31
Reserved
Reserved
1. Only if ETRIG3-0 input option is available (see device specification), else ETRISEL is ignored, that means
external trigger source is still on one of the AD channels selected by ETRIGCH3-0
S12P-Family Reference Manual, Rev. 1.13
312
Freescale Semiconductor
FREESCALE [ Freescale ]
