Analog-to-Digital Converter (ADC12B10C)
9.2
Signal Description
This section lists all inputs to the ADC12B10C block.
9.2.1
Detailed Signal Descriptions
9.2.1.1
ANx (x = 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)
This pin serves as the analog input Channel x. It can also be configured as digital port or external trigger
for the ATD conversion.
9.2.1.2
ETRIG3, ETRIG2, ETRIG1, ETRIG0
These inputs can be configured to serve as an external trigger for the ATD conversion.
Refer to device specification for availability and connection of these inputs!
9.2.1.3
VRH, VRL
V
is the high reference voltage, V is the low reference voltage for ATD conversion.
RL
RH
9.2.1.4
VDDA, VSSA
These pins are the power supplies for the analog circuitry of the ADC12B10C block.
9.3
Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the ADC12B10C.
9.3.1
Module Memory Map
Figure 9-2 gives an overview on all ADC12B10C registers.
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
Address
Name
Bit 7
6
5
4
3
2
1
Bit 0
R
W
R
0
0
0
0x0000
ATDCTL0
Reserved
WRAP3
WRAP2
WRAP1
WRAP0
0x0001
0x0002
ATDCTL1
ATDCTL2
ETRIGSEL SRES1
SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0
ICLKSTP ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE
W
R
0
AFFC
W
= Unimplemented or Reserved
Figure 9-2. ADC12B10C Register Summary (Sheet 1 of 3)
S12P-Family Reference Manual, Rev. 1.13
308
Freescale Semiconductor
FREESCALE [ Freescale ]
