Analog-to-Digital Converter (ADC12B10C)
Table 9-2. Multi-Channel Wrap Around Coding
Multiple Channel Conversions (MULT = 1)
WRAP3 WRAP2 WRAP1 WRAP0
Wraparound to AN0 after Converting
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
AN6
AN7
AN8
AN9
AN9
AN9
AN9
AN9
AN9
AN9
1. If only AN0 should be converted use MULT=0.
9.3.2.2
ATD Control Register 1 (ATDCTL1)
Writes to this register will abort current conversion sequence.
Module Base + 0x0001
7
6
5
4
3
2
1
0
R
W
ETRIGSEL
SRES1
SRES0
SMP_DIS
ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0
Reset
0
0
1
0
1
1
1
1
Figure 9-4. ATD Control Register 1 (ATDCTL1)
Read: Anytime
Write: Anytime
Table 9-3. ATDCTL1 Field Descriptions
Description
Field
7
External Trigger Source Select — This bit selects the external trigger source to be either one of the AD
ETRIGSEL channels or one of the ETRIG3-0 inputs. See device specification for availability and connectivity of ETRIG3-
0 inputs. If a particular ETRIG3-0 input option is not available, writing a 1 to ETRISEL only sets the bit but has
not effect, this means that one of the AD channels (selected by ETRIGCH3-0) is configured as the source for
external trigger. The coding is summarized in Table 9-5.
6–5
A/D Resolution Select — These bits select the resolution of A/D conversion results. See Table 9-4 for coding.
SRES[1:0]
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
311
FREESCALE [ Freescale ]
