Analog-to-Digital Converter (ADC12B10C)
Table 9-6. ATDCTL2 Field Descriptions (continued)
Field
Description
1
ATD Sequence Complete Interrupt Enable
ASCIE
0 ATD Sequence Complete interrupt requests are disabled.
1 ATD Sequence Complete interrupt will be requested whenever SCF=1 is set.
0
ATD Compare Interrupt Enable — If automatic compare is enabled for conversion n (CMPE[n]=1 in ATDCMPE
register) this bit enables the compare interrupt. If the CCF[n] flag is set (showing a successful compare for
conversion n), the compare interrupt is triggered.
ACMPIE
0 ATD Compare interrupt requests are disabled.
1 For the conversions in a sequence for which automatic compare is enabled (CMPE[n]=1), ATD Compare
Interrupt will be requested whenever any of the respective CCF flags is set.
Table 9-7. External Trigger Configurations
ETRIGLE
ETRIGP
External Trigger Sensitivity
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Low level
High level
9.3.2.4
ATD Control Register 3 (ATDCTL3)
Writes to this register will abort current conversion sequence.
Module Base + 0x0003
7
6
5
4
3
2
1
0
R
W
DJM
S8C
S4C
S2C
S1C
FIFO
FRZ1
FRZ0
Reset
0
0
1
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-6. ATD Control Register 3 (ATDCTL3)
Read: Anytime
Write: Anytime
S12P-Family Reference Manual, Rev. 1.13
314
Freescale Semiconductor
FREESCALE [ Freescale ]
