Analog-to-Digital Converter (ADC12B10C)
Address
Name
Bit 7
6
5
4
3
2
1
Bit 0
R
W
R
0x0003
ATDCTL3
DJM
S8C
S4C
S2C
S1C
FIFO
FRZ1
FRZ0
0x0004
0x0005
0x0006
0x0007
ATDCTL4
ATDCTL5
ATDSTAT0
SMP2
0
SMP1
SMP0
SCAN
PRS[4:0]
W
R
SC
0
MULT
CD
CC
CB
CA
W
R
CC3
CC2
CC1
CC0
SCF
0
ETORF
0
FIFOR
0
W
R
0
0
0
0
0
0
0
0
Unimple-
mented
W
R
0
0
0
0
0
0
0
0
0
0x0008 ATDCMPEH
0x0009 ATDCMPEL
0x000A ATDSTAT2H
0x000B ATDSTAT2L
0x000C ATDDIENH
0x000D ATDDIENL
0x000E ATDCMPHTH
0x000F ATDCMPHTL
CMPE[9:8]
W
R
CMPE[7:0]
W
R
0
0
0
0
0
0
0
0
0
0
CCF[9:8]
W
R
CCF[7:0]
W
R
0
0
IEN[9:8]
W
R
IEN[7:0]
W
R
CMPHT[9:8]
W
R
CMPHT[7:0]
W
R
See Section 9.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 9.3.2.12.2, “Right Justified Result Data (DJM=1)”
0x0010
0x0012
0x0014
0x0016
0x0018
0x001A
0x001C
0x001E
ATDDR0
ATDDR1
ATDDR2
ATDDR3
ATDDR4
ATDDR5
ATDDR6
ATDDR7
W
R
See Section 9.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 9.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
R
See Section 9.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 9.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
R
See Section 9.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 9.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
R
See Section 9.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 9.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
R
See Section 9.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 9.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
R
See Section 9.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 9.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
R
See Section 9.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 9.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
= Unimplemented or Reserved
Figure 9-2. ADC12B10C Register Summary (Sheet 2 of 3)
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
309
FREESCALE [ Freescale ]
