Analog-to-Digital Converter (ADC12B10C)
•
Configurable external trigger functionality on any AD channel or any of four additional trigger
inputs. The four additional trigger inputs can be chip external or internal. Refer to device
specification for availability and connectivity.
•
Configurable location for channel wrap around (when converting multiple channels in a sequence).
9.1.2
Modes of Operation
9.1.2.1
Conversion Modes
There is software programmable selection between performing single or continuous conversion on a
single channel or multiple channels.
9.1.2.2
MCU Operating Modes
•
Stop Mode
— ICLKSTP=0 (in ATDCTL2 register)
Entering Stop Mode aborts any conversion sequence in progress and if a sequence was aborted
restarts it after exiting stop mode. This has the same effect/consequences as starting a
conversion sequence with write to ATDCTL5. So after exiting from stop mode with a
previously aborted sequence all flags are cleared etc.
— ICLKSTP=1 (in ATDCTL2 register)
A/D conversion sequence seamless continues in Stop Mode based on the internally generated
clock ICLK as ATD clock. For conversions during transition from Run to Stop Mode or vice
versa the result is not written to the results register, no CCF flag is set and no compare is done.
When converting in Stop Mode (ICLKSTP=1) an ATD Stop Recovery time tATDSTPRCV is
required to switch back to bus clock based ATDCLK when leaving Stop Mode. Do not access
ATD registers during this time.
•
•
Wait Mode
ADC12B10C behaves same in Run and Wait Mode. For reduced power consumption continuous
conversions should be aborted before entering Wait mode.
Freeze Mode
In Freeze Mode the ADC12B10C will either continue or finish or stop converting according to the
FRZ1 and FRZ0 bits. This is useful for debugging and emulation.
S12P-Family Reference Manual, Rev. 1.13
306
Freescale Semiconductor
FREESCALE [ Freescale ]
