Port Integration Module (S12PPIMV1)
Port E pin PE[0] can be used for either general purpose input or as the level-sensitive XIRQ interrupt input.
XIRQ can be enabled by clearing the X-bit in the CPU condition code register. It is inhibited at reset so
this pin is initially configured as a high-impedance input with a pull-up.
2.4.3.4
Port T
This port is associated with TIM and PWM.
Port T pins PT[5:4,0] can be used for either general purpose I/O, or with the routed PWM or with the
channels of the standard Timer subsystem.
Port T pins PT[7:6,3:1] can be used for either general purpose I/O, or with the channels of the standard
Timer subsystem.
2.4.3.5
Port S
This port is associated with SCI.
Port S pins PS[1:0] can be used either for general purpose I/O, or with the SCI subsystem.
Port S pins PS[3:2] can be used for general purpose I/O.
2.4.3.6
Port M
This port is associated with CAN and SPI.
Port M pins PM[1:0] can be used for either general purpose I/O, or with the CAN subsystem.
Port M pins PM[5:2] can be used for general purpose I/O, or with the SPI subsystem.
2.4.3.7
Port P
This port is associated with the PWM.
Port P pins PP[7,5:0] can be used for either general purpose I/O with pin interrupt capability, or with the
PWM subsystem.
2.4.3.8
Port J
Port J pins PJ[7:6,2:0] can be used for general purpose I/O with pin-interrupt capability.
2.4.3.9
Port AD
This port is associated with the ATD.
Port AD pins PAD[9:0] can be used for either general purpose I/O, or with the ATD subsystem.
S12P-Family Reference Manual, Rev. 1.13
104
Freescale Semiconductor
FREESCALE [ Freescale ]
