Chapter 3
Memory Map Control (S12PMMCV1)
Table 3-1. Revision History Table
Table 3-2.
Rev. No.
(Item No.) (Submitted By)
Date
Sections
Affected
Substantial Change(s)
01.03
01.04
01.05
10.JAN.2008
13.JAN.2010
22.APR.2010
General
Figure 3-2
General
Minor Changes
Added reserved registers
Removed references to the MMCCTL1 register
3.1
Introduction
The S12PMMC module controls the access to all internal memories and peripherals for the CPU12 and
S12SBDM module. It regulates access priorities and determines the address mapping of the on-chip
ressources. Figure 3-1 shows a block diagram of the S12PMMC module.
3.1.1
Glossary
Table 3-3. Glossary Of Terms
Term
Definition
Local Addresses
Address within the CPU12’s Local Address Map (Figure 3-10)
Address within the Global Address Map (Figure 3-10)
Bus access to an even address.
Global Addresse
Aligned Bus Access
Misaligned Bus Access
Bus access to an odd address.
NS
Normal Single-Chip Mode
SS
Special Single-Chip Mode
Unimplemented Address Ranges
Address ranges which are not mapped to any on-chip ressource.
Program Flash
P-Flash
D-Plash
NVM
Data Flash
Non-volatile Memory; P-Flash or D-Flash
NVM Information Row. Refer to FTMRC Block Guide
IFR
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
107
FREESCALE [ Freescale ]
