Port Integration Module (S12PPIMV1)
For example selecting a pull-up device: This device does not become active while the port is used as a
push-pull output.
(1)
Table 2-59. Register availability per port
Data
Direction
Reduced
Drive
Pull
Enable
Polarity
Select
Wired-
Or Mode
Interrupt Interrupt
Port
Data
Input
Routing
Enable
Flag
A
B
yes
yes
yes
yes
yes
yes
yes
yes
yes
-
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
-
-
-
-
-
-
-
-
-
-
-
E
-
-
-
-
-
-
T
yes
yes
yes
yes
yes
-
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
-
-
yes
yes
-
-
-
-
-
yes
S
-
M
P
-
-
yes
yes
yes
-
yes
yes
-
-
-
-
J
-
AD
-
1. Each cell represents one register with individual configuration bits
2.4.2.1
Data register (PORTx, PTx)
This register holds the value driven out to the pin if the pin is used as a general purpose I/O.
Writing to this register has only an effect on the pin if the pin is used as general purpose output. When
reading this address, the buffered state of the pin is returned if the associated data direction register bit is
set to “0”.
If the data direction register bits are set to logic level “1”, the contents of the data register is returned. This
is independent of any other configuration (Figure 2-64).
2.4.2.2
Input register (PTIx)
This register is read-only and always returns the buffered state of the pin (Figure 2-64).
2.4.2.3
Data direction register (DDRx)
This register defines whether the pin is used as an general purpose input or an output.
If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 2-64).
Independent of the pin usage with a peripheral module this register determines the source of data when
reading the associated data register address (2.4.2.1/2-101).
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on port data or port input registers, when
changing the data direction register.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
101
FREESCALE [ Freescale ]
