Port Integration Module (S12PPIMV1)
2.4.4
Pin interrupts
Ports P and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or falling
edges can be individually configured on per-pin basis. All bits/pins in a port share the same interrupt
vector. Interrupts can be used with the pins configured as inputs or outputs.
An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt
enable bit are both set. The pin interrupt feature is also capable to wake up the CPU when it is in STOP or
WAIT mode.
A digital filter on each pin prevents pulses (Figure 2-66) shorter than a specified time from generating an
interrupt. The minimum time varies over process conditions, temperature and voltage (Figure 2-65 and
Table 2-60).
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
uncertain
t
pign
t
pval
Figure 2-65. Interrupt Glitch Filter on Port P and J (PPS=0)
Table 2-60. Pulse Detection Criteria
Mode
(1)
Pulse
STOP
STOP
Unit
tpulse ≤ 3
tpulse ≤ tpign
Ignored
Uncertain
Valid
bus clocks
bus clocks
bus clocks
3 < tpulse < 4
tpign < tpulse < tpval
tpulse ≥ 4
tpulse ≥ tpval
1. These values include the spread of the oscillator frequency over temperature,
voltage and process.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
105
FREESCALE [ Freescale ]
