Clock Generator Module (CGM)
Functional Description
for the base clock. See 4.3.3 Base Clock Selector Circuit. If the VCO is selected
as the source for the base clock and the LOCK bit is clear, the PLL has suffered a
severe noise hit and the software must take appropriate action, depending on the
application. See 4.6 Interrupts for information and precautions on using interrupts.
These conditions apply when the PLL is in automatic bandwidth control mode:
•
•
The ACQ bit (see 4.5.2 PLL Bandwidth Control Register) is a read-only
indicator of the mode of the filter. For more information, see 4.3.2.2
Acquisition and Tracking Modes.
The ACQ bit is set when the VCO frequency is within a certain tolerance,
∆
∆
TRK, and is cleared when the VCO frequency is out of a certain tolerance,
UNT. For more information, see 4.8 Acquisition/Lock Time
Specifications.
•
•
The LOCK bit is a read-only indicator of the locked state of the PLL.
The LOCK bit is set when the VCO frequency is within a certain tolerance,
∆
∆
Lock, and is cleared when the VCO frequency is out of a certain tolerance,
UNL. For more information, see 4.8 Acquisition/Lock Time
Specifications.
•
CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock
condition changes, toggling the LOCK bit. For more information, see 4.5.1
PLL Control Register.
The PLL also may operate in manual mode (AUTO = 0). Manual mode is used by
systems that do not require an indicator of the lock condition for proper operation.
Such systems typically operate well below fBUSMAX and require fast startup. These
conditions apply when in manual mode:
•
ACQ is a writable control bit that controls the mode of the filter. Before
turning on the PLL in manual mode, the ACQ bit must be clear.
•
Before entering tracking mode (ACQ = 1), software must wait a given time,
tACQ (see 4.8 Acquisition/Lock Time Specifications), after turning on the
PLL by setting PLLON in the PLL control register (PCTL).
•
Software must wait a given time, tAL, after entering tracking mode before
selecting the PLL as the clock source to CGMOUT (BCS = 1).
•
•
The LOCK bit is disabled.
CPU interrupts from the CGM are disabled.
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA Clock Generator Module (CGM)
Data Sheet
63
FREESCALE [ Freescale ]
