Clock Generator Module (CGM)
clock by a factor, N. The divider’s output is the VCO feedback clock, CGMVDV,
running at a frequency, fVDV = fVCLK/N. (See 4.3.2.4 Programming the PLL for
more information.)
The phase detector then compares the VCO feedback clock, CGMVDV, with the
final reference clock, CGMRDV. A correction pulse is generated based on the
phase difference between the two signals. The loop filter then slightly alters the dc
voltage on the external capacitor connected to CGMXFC based on the width and
direction of the correction pulse. The filter can make fast or slow corrections
depending on its mode, described in 4.3.2.2 Acquisition and Tracking Modes.
The value of the external capacitor and the reference frequency determines the
speed of the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock, CGMVDV,
and the final reference clock, CGMRDV. Therefore, the speed of the lock detector
is directly proportional to the final reference frequency, fRDV. The circuit determines
the mode of the PLL and the lock condition based on this comparison.
4.3.2.2 Acquisition and Tracking Modes
The PLL filter is manually or automatically configurable into one of two operating
modes:
1. Acquisition mode — In acquisition mode, the filter can make large frequency
corrections to the VCO. This mode is used at PLL startup or when the PLL
has suffered a severe noise hit and the VCO frequency is far off the desired
frequency. When in acquisition mode, the ACQ bit is clear in the PLL
bandwidth control register. See 4.5.2 PLL Bandwidth Control Register.
2. Tracking mode — In tracking mode, the filter makes only small corrections
to the frequency of the VCO. PLL jitter is much lower in tracking mode, but
the response to noise is also slower. The PLL enters tracking mode when
the VCO frequency is nearly correct, such as when the PLL is selected as
the base clock source. See 4.3.3 Base Clock Selector Circuit. The PLL is
automatically in tracking mode when not in acquisition mode or when the
ACQ bit is set.
4.3.2.3 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter manually
or automatically.
In automatic bandwidth control mode (AUTO = 1), the lock detector automatically
switches between acquisition and tracking modes. Automatic bandwidth control
mode also is used to determine when the VCO clock, CGMVCLK, is safe to use as
the source for the base clock, CGMOUT. See 4.5.2 PLL Bandwidth Control
Register. If PLL interrupts are enabled, the software can wait for a PLL interrupt
request and then check the LOCK bit. If interrupts are disabled, software can poll
the LOCK bit continuously (during PLL startup, usually) or at periodic intervals. In
either case, when the LOCK bit is set, the VCO clock is safe to use as the source
Data Sheet
62
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
Clock Generator Module (CGM)
MOTOROLA
FREESCALE [ Freescale ]
