Clock Generator Module (CGM)
CRYSTAL OSCILLATOR
OSC2
CGMXCLK
CGMOUT
TO SIM
TO SIM
CLOCK
SELECT
CIRCUIT
OSC1
A
B
÷ 2
S*
*WHEN S = 1, CGMOUT = B
SIMOSCEN
CGMRDV
CGMRCLK
BCS
USER MODE
VDDA
CGMXFC
VSS
PTC2
VRS[7:4]
MONITOR MODE
VOLTAGE
CONTROLLED
OSCILLATOR
PHASE
DETECTOR
LOOP
FILTER
PLL ANALOG
CGMINT
LOCK
DETECTOR
BANDWIDTH
CONTROL
INTERRUPT
CONTROL
LOCK
AUTO
ACQ
PLLIE
PLLF
MUL[7:4]
CGMVDV
CGMVCLK
FREQUENCY
DIVIDER
Figure 4-1. CGM Block Diagram
Addr.
Register Name
Bit 7
PLLIE
0
6
PLLF
R
5
PLLON
1
4
BCS
0
3
2
1
1
1
Bit 0
Read:
1
R
1
1
R
1
PLL Control Register
(PCTL) Write:
$005C
R
1
R
1
See page 69.
Reset:
Read:
0
LOCK
R
0
0
0
0
PLL Bandwidth Control Register
AUTO
0
ACQ
0
XLD
0
$005D
$005E
(PBWC) Write:
R
0
R
0
R
0
R
0
See page 71.
Reset:
Read:
0
PLL Programming Register
MUL7
MUL6
MUL5
1
MUL4
0
VRS7
0
VRS6
1
VRS5
1
VRS4
0
(PPG) Write:
See page 72.
Reset:
0
1
R
= Reserved
Figure 4-2. CGM I/O Register Summary
Data Sheet
60
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
Clock Generator Module (CGM) MOTOROLA
FREESCALE [ Freescale ]
