Timer Interface B (TIMB)
I/O Registers
Register Name and Address:
Bit 7
TBSC0 — $0056
5
6
CH0IE
0
4
3
ELS0B
0
2
ELS0A
0
1
TOV0
0
Bit 0
CH0MAX
0
Read:
Write:
Reset:
CH0F
MS0B
0
MS0A
0
0
0
Register Name and Address:
Bit 7
TBSC1 — $0059
6
5
0
4
3
ELS1B
0
2
ELS1A
0
1
TOV1
0
Bit 0
CH1MAX
0
Read:
Write:
Reset:
CH1F
CH1IE
MS1A
0
0
0
R
0
0
R
= Reserved
Figure 17-8. TIMB Channel Status
and Control Registers (TBSC0–TBSC1)
CHxF — Channel x Flag
When channel x is an input capture channel, this read/write bit is set when an
active edge occurs on the channel x pin. When channel x is an output compare
channel, CHxF is set when the value in the TIMB counter registers matches the
value in the TIMB channel x registers.
When CHxIE = 1, clear CHxF by reading TIMB channel x status and control
register with CHxF set, and then writing a 0 to CHxF. If another interrupt request
occurs before the clearing sequence is complete, then writing 0 to CHxF has no
effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing
of CHxF.
Reset clears the CHxF bit. Writing a 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIMB CPU interrupts on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation. MSxB
exists only in the TIMB channel 0.
Setting MS0B disables the channel 1 status and control register and reverts
TCH1B to general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA Timer Interface B (TIMB)
Data Sheet
269
FREESCALE [ Freescale ]
