Data Sheet — MC68HC908MR32 • MC68HC908MR16
Section 18. Development Support
18.1 Introduction
This section describes the break module, the monitor read-only memory (MON),
and the monitor mode entry methods.
18.2 Break Module (BRK)
The break module (BRK) can generate a break interrupt that stops normal program
flow at a defined address to enter a background program. Features include:
•
•
•
•
Accessible input/output (I/O) registers during the break interrupt
Central processor unit (CPU) generated break interrupts
Software-generated break interrupts
Computer operating properly (COP) disabling during break interrupts
18.2.1 Functional Description
When the internal address bus matches the value written in the break address
registers, the break module issues a breakpoint signal to the CPU. The CPU then
loads the instruction register with a software interrupt instruction (SWI) after
completion of the current CPU instruction. The program counter vectors to $FFFC
and $FFFD ($FEFC and $FEFD in monitor mode).
These events can cause a break interrupt to occur:
•
A CPU-generated address (the address in the program counter) matches
the contents of the break address registers.
•
Software writes a logic 1 to the BRKA bit in the break status and control
register.
When a CPU-generated address matches the contents of the break address
registers, the break interrupt begins after the CPU completes its current instruction.
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the microcontroller unit (MCU) to normal operation.
Figure 18-1 shows the structure of the break module.
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA
Data Sheet
273
Development Support
FREESCALE [ Freescale ]
