Timer Interface B (TIMB)
17.7.5 TIMB Channel Registers
These read/write registers contain the captured TIMB counter value of the input
capture function or the output compare value of the output compare function. The
state of the TIMB channel registers after reset is unknown.
In input capture mode (MSxB–MSxA = 0:0), reading the high byte of the TIMB
channel x registers (TBCHxH) inhibits input captures until the low byte (TBCHxL)
is read.
In output compare mode (MSxB–MSxA ≠ 0:0), writing to the high byte of the TIMB
channel x registers (TBCHxH) inhibits output compares until the low byte
(TBCHxL) is written.
Register Name and Address:
Bit 7
TBCH0H — $0057
6
5
4
3
2
1
Bit 0
Bit 8
Read:
Bit 15
Write:
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Reset:
Indeterminate after reset
Register Name and Address:
Bit 7
TBCH0L — $0058
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Bit 7
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Reset:
Indeterminate after reset
Register Name and Address:
Bit 7
TBCH1H — $005A
6
5
4
3
2
1
Bit 0
Bit 8
Read:
Bit 15
Write:
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Reset:
Indeterminate after reset
Register Name and Address:
Bit 7
TBCH1L — $005B
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Bit 7
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Reset:
Indeterminate after reset
Figure 17-10. TIMB Channel Registers
(TBCH0H/L–TBCH1H/L)
Data Sheet
272
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA
Timer Interface B (TIMB)
FREESCALE [ Freescale ]
