Timer Interface B (TIMB)
I/O Registers
Table 17-1. Prescaler Selection
PS[2:0]
000
TIMB Clock Source
Internal bus clock ÷1
Internal bus clock ÷ 2
Internal bus clock ÷ 4
Internal bus clock ÷ 8
Internal bus clock ÷ 16
Internal bus clock ÷ 32
Internal bus clock ÷ 64
PTE0/TCLKB
001
010
011
100
101
110
111
17.7.2 TIMB Counter Registers
The two read-only TIMB counter registers contain the high and low bytes of the
value in the TIMB counter. Reading the high byte (TBCNTH) latches the contents
of the low byte (TBCNTL) into a buffer. Subsequent reads of TBCNTH do not affect
the latched TBCNTL value until TBCNTL is read. Reset clears the TIMB counter
registers. Setting the TIMB reset bit (TRST) also clears the TIMB counter registers.
NOTE:
If TBCNTH is read during a break interrupt, be sure to unlatch TBCNTL by reading
TBCNTL before exiting the break interrupt. Otherwise, TBCNTL retains the value
latched during the break.
Register Name and Address:
Bit 7
TBCNTH — $0052
6
Bit 14
R
5
Bit 13
R
4
3
Bit 11
R
2
Bit 10
R
1
Bit 9
R
Bit 0
Bit 8
R
Read:
Write:
Reset:
Bit 15
Bit 12
R
0
R
0
0
0
0
0
0
0
Register Name and Address:
Bit 7
TBCNTL — $0053
6
5
Bit 5
R
4
3
Bit 3
R
2
Bit 2
R
1
Bit 1
R
Bit 0
Bit 0
R
Read:
Write:
Reset:
Bit 7
R
Bit 6
Bit 4
R
R
0
0
0
0
0
0
0
0
R
= Reserved
Figure 17-6. TIMB Counter Registers (TBCNTH and TBCNTL)
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA
Data Sheet
267
Timer Interface B (TIMB)
FREESCALE [ Freescale ]
