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MC908MR32CFUE 参数 Datasheet PDF下载

MC908MR32CFUE图片预览
型号: MC908MR32CFUE
PDF下载: 下载PDF文件 查看货源
内容描述: [MC908MR32CFUE ]
分类和应用:
文件页数/大小: 308 页 / 4411 K
品牌: FREESCALE [ Freescale ]
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Timer Interface B (TIMB)  
then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt request  
cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit.  
Writing a logic 1 to TOF has no effect.  
1 = TIMB counter has reached modulo value.  
0 = TIMB counter has not reached modulo value.  
TOIE — TIMB Overflow Interrupt Enable Bit  
This read/write bit enables TIMB overflow interrupts when the TOF bit becomes  
set. Reset clears the TOIE bit.  
1 = TIMB overflow interrupts enabled  
0 = TIMB overflow interrupts disabled  
TSTOP — TIMB Stop Bit  
This read/write bit stops the TIMB counter. Counting resumes when TSTOP is  
cleared. Reset sets the TSTOP bit, stopping the TIMB counter until software  
clears the TSTOP bit.  
1 = TIMB counter stopped  
0 = TIMB counter active  
NOTE:  
Do not set the TSTOP bit before entering wait mode if the TIMB is required to exit  
wait mode. Also, when the TSTOP bit is set and the timer is configured for input  
capture operation, input captures are inhibited until TSTOP is cleared.  
TRST — TIMB Reset Bit  
Setting this write-only bit resets the TIMB counter and the TIMB prescaler.  
Setting TRST has no effect on any other registers. Counting resumes from  
$0000. TRST is cleared automatically after the TIMB counter is reset and  
always reads as logic 0. Reset clears the TRST bit.  
1 = Prescaler and TIMB counter cleared  
0 = No effect  
NOTE:  
Setting the TSTOP and TRST bits simultaneously stops the TIMB counter at a  
value of $0000.  
PS[2:0] — Prescaler Select Bits  
These read/write bits select either the PTE0/TCLKB pin or one of the seven  
prescaler outputs as the input to the TIMB counter as Table 17-1 shows. Reset  
clears the PS[2:0] bits.  
Data Sheet  
266  
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0  
Timer Interface B (TIMB)  
MOTOROLA  
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