Timer Interface B (TIMB)
17.3.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare pulses as
described in 17.3.3 Output Compare. The pulses are unbuffered because
changing the output compare value requires writing the new value over the old
value currently in the TIMB channel registers.
An unsynchronized write to the TIMB channel registers to change an output
compare value could cause incorrect operation for up to two counter overflow
periods. For example, writing a new value before the counter reaches the old value
but after the counter reaches the new value prevents any compare during that
counter overflow period. Also, using a TIMB overflow interrupt routine to write a
new, smaller output compare value may cause the compare to be missed. The
TIMB may pass the new value before it is written.
Use this method to synchronize unbuffered changes in the output compare value
on channel x:
•
When changing to a smaller value, enable channel x output compare
interrupts and write the new value in the output compare interrupt routine.
The output compare interrupt occurs at the end of the current output
compare pulse. The interrupt routine has until the end of the counter
overflow period to write the new value.
•
When changing to a larger output compare value, enable TIMB overflow
interrupts and write the new value in the TIMB overflow interrupt routine. The
TIMB overflow interrupt occurs at the end of the current counter overflow
period. Writing a larger value in an output compare interrupt routine (at the
end of the current pulse) could cause two output compares to occur in the
same counter overflow period.
17.3.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose
output appears on the PTE1/TCH0B pin. The TIMB channel registers of the linked
pair alternately control the output.
Setting the MS0B bit in TIMB channel 0 status and control register (TBSC0) links
channel 0 and channel 1. The output compare value in the TIMB channel 0
registers initially controls the output on the PTE1/TCH0B pin. Writing to the TIMB
channel 1 registers enables the TIMB channel 1 registers to synchronously control
the output after the TIMB overflows. At each subsequent overflow, the TIMB
channel registers (0 or 1) that control the output are the ones written to last. TSC0
controls and monitors the buffered output compare function, and TIMB channel 1
status and control register (TBSC1) is unused. While the MS0B bit is set, the
channel 1 pin, PTE2/TCH1B, is available as a general-purpose I/O pin.
NOTE:
In buffered output compare operation, do not write new output compare values to
the currently active channel registers. User software should track the currently
Data Sheet
260
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
Timer Interface B (TIMB)
MOTOROLA
FREESCALE [ Freescale ]
