System Integration Module (SIM)
Reset and System Initialization
14.3.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to
allow resetting of external peripherals. The internal reset signal (IRST) continues
to be asserted for an additional 32 cycles (see Figure 14-5). An internal reset can
be caused by an illegal address, illegal opcode, COP timeout, LVI, or POR. (See
Figure 14-4.)
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
INTERNAL RESET
POR
Figure 14-4. Sources of Internal Reset
NOTE:
For LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles during
which the SIM forces the RST pin low. The internal reset signal then follows the
sequence from the falling edge of RST, as shown in Figure 14-5.
IRST
RST PULLED LOW BY MCU
32 CYCLES
RST
32 CYCLES
CGMXCLK
IAB
VECTOR HIGH
Figure 14-5. Internal Reset Timing
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals and other
chips within a system built around the MCU.
14.3.2.1 Power-On Reset (POR)
When power is first applied to the MCU, the power-on reset (POR) module
generates a pulse to indicate that power-on has occurred. The external reset pin
(RST) is held low while the SIM counter counts out 4096 CGMXCLK cycles.
Sixty-four CGMXCLK cycles later, the CPU and memories are released from reset
to allow the reset vector sequence to occur.
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA System Integration Module (SIM)
Data Sheet
199
FREESCALE [ Freescale ]
