System Integration Module (SIM)
MODULE WAIT
WAIT
CONTROL
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM)
SIM
COUNTER
COP CLOCK
CGMXCLK (FROM CGM)
CGMOUT (FROM CGM)
÷ 2
CLOCK
CONTROL
CLOCK GENERATORS
INTERNAL CLOCKS
LVI (FROM LVI MODULE)
RESET
PIN LOGIC
POR CONTROL
MASTER
RESET
CONTROL
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
RESET PIN CONTROL
SIM RESET STATUS REGISTER
COP (FROM COP MODULE)
RESET
INTERRUPT SOURCES
CPU INTERFACE
INTERRUPT CONTROL
AND PRIORITY DECODE
Figure 14-1. SIM Block Diagram
Table 14-1. Signal Name Conventions
Signal Name
CGMXCLK
CGMVCLK
CGMOUT
IAB
Description
Buffered version of OSC1 from clock generator module (CGM)
Phase-locked loop (PLL) circuit output
PLL-based or OSC1-based clock output from CGM module (bus clock = CGMOUT divided by two)
Internal address bus
IDB
Internal data bus
PORRST
IRST
Signal from the power-on reset module to the SIM
Internal reset signal
R/W
Read/write signal
Data Sheet
196
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
System Integration Module (SIM)
MOTOROLA
FREESCALE [ Freescale ]
