Serial Communications Interface Module (SCI)
FEIE — Receiver Framing Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests generated by the
framing error bit, FE. Reset clears FEIE.
1 = SCI error CPU interrupt requests from FE bit enabled
0 = SCI error CPU interrupt requests from FE bit disabled
PEIE — Receiver Parity Error Interrupt Enable Bit
This read/write bit enables SCI receiver CPU interrupt requests generated by
the parity error bit, PE. See 13.7.4 SCI Status Register 1. Reset clears PEIE.
1 = SCI error CPU interrupt requests from PE bit enabled
0 = SCI error CPU interrupt requests from PE bit disabled
13.7.4 SCI Status Register 1
SCI status register 1 (SCS1) contains flags to signal these conditions:
•
•
•
•
•
•
•
•
Transfer of SCDR data to transmit shift register complete
Transmission complete
Transfer of receive shift register data to SCDR complete
Receiver input idle
Receiver overrun
Noisy data
Framing error
Parity error
Address: $003B
Bit 7
6
5
SCRF
R
4
IDLE
R
3
OR
R
2
NF
R
1
FE
R
Bit 0
PE
R
Read:
Write:
Reset:
SCTE
TC
R
1
R
1
0
0
0
0
0
0
R
= Reserved
Figure 13-11. SCI Status Register 1 (SCS1)
SCTE — SCI Transmitter Empty Bit
This clearable, read-only bit is set when the SCDR transfers a character to the
transmit shift register. SCTE can generate an SCI transmitter CPU interrupt
request. When the SCTIE bit in SCC2 is set, SCTE generates an SCI transmitter
CPU interrupt request. In normal operation, clear the SCTE bit by reading SCS1
with SCTE set and then writing to SCDR. Reset sets the SCTE bit.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
Data Sheet
188
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
Serial Communications Interface Module (SCI)
MOTOROLA
FREESCALE [ Freescale ]
