Serial Communications Interface Module (SCI)
13.7.6 SCI Data Register
The SCI data register (SCDR) is the buffer between the internal data bus and the
receive and transmit shift registers. Reset has no effect on data in the SCI data
register.
Address:
$003D
Bit 7
R7
6
5
4
3
2
1
Bit 0
R0
Read:
Write:
Reset:
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
T7
T0
Unaffected by reset
Figure 13-14. SCI Data Register (SCDR)
R7/T7:R0/T0 — Receive/Transmit Data Bits
Reading address $003D accesses the read-only received data bits, R7:R0.
Writing to address $003D writes the data to be transmitted, T7:T0. Reset has no
effect on the SCI data register.
13.7.7 SCI Baud Rate Register
The baud rate register (SCBR) selects the baud rate for both the receiver and the
transmitter.
Address:
$003E
Bit 7
0
6
5
SCP1
0
4
SCP0
0
3
0
2
SCR2
0
1
SCR1
0
Bit 0
SCR0
0
Read:
Write:
Reset:
0
R
R
R
0
0
0
R
= Reserved
Figure 13-15. SCI Baud Rate Register (SCBR)
SCP1 and SCP0 — SCI Baud Rate Prescaler Bits
These read/write bits select the baud rate prescaler divisor as shown in Table
13-5. Reset clears SCP1 and SCP0.
Table 13-5. SCI Baud Rate Prescaling
SCP1:SCP0
Prescaler Divisor (PD)
00
01
10
11
1
3
4
13
Data Sheet
192
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
Serial Communications Interface Module (SCI)
MOTOROLA
FREESCALE [ Freescale ]
