Serial Communications Interface Module (SCI)
I/O Registers
13.7.2 SCI Control Register 2
SCI control register 2 (SCC2):
•
Enables these CPU interrupt requests:
–
–
–
–
Enables the SCTE bit to generate transmitter CPU interrupt requests
Enables the TC bit to generate transmitter CPU interrupt requests
Enables the SCRF bit to generate receiver CPU interrupt requests
Enables the IDLE bit to generate receiver CPU interrupt requests
•
•
•
•
Enables the transmitter
Enables the receiver
Enables SCI wakeup
Transmits SCI break characters
Address: $0039
Bit 7
6
TCIE
0
5
SCRIE
0
4
ILIE
0
3
TE
0
2
RE
0
1
RWU
0
Bit 0
SBK
0
Read:
Write:
Reset:
SCTIE
0
Figure 13-9. SCI Control Register 2 (SCC2)
SCTIE — SCI Transmit Interrupt Enable Bit
This read/write bit enables the SCTE bit to generate SCI transmitter CPU
interrupt requests. Setting the SCTIE bit in SCC3 enables SCTE CPU interrupt
requests. Reset clears the SCTIE bit.
1 = SCTE enabled to generate CPU interrupt
0 = SCTE not enabled to generate CPU interrupt
TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables the TC bit to generate SCI transmitter CPU interrupt
requests. Reset clears the TCIE bit.
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
SCRIE — SCI Receive Interrupt Enable Bit
This read/write bit enables the SCRF bit to generate SCI receiver CPU interrupt
requests. Setting the SCRIE bit in SCC3 enables the SCRF bit to generate CPU
interrupt requests. Reset clears the SCRIE bit.
1 = SCRF enabled to generate CPU interrupt
0 = SCRF not enabled to generate CPU interrupt
ILIE — Idle Line Interrupt Enable Bit
This read/write bit enables the IDLE bit to generate SCI receiver CPU interrupt
requests. Reset clears the ILIE bit.
1 = IDLE enabled to generate CPU interrupt requests
0 = IDLE not enabled to generate CPU interrupt requests
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA Serial Communications Interface Module (SCI)
Data Sheet
185
FREESCALE [ Freescale ]
