Serial Communications Interface Module (SCI)
I/O Registers
13.7.3 SCI Control Register 3
SCI control register 3 (SCC3):
•
Stores the ninth SCI data bit received and the ninth SCI data bit to be
transmitted
•
•
•
Enables SCI receiver full (SCRF)
Enables SCI transmitter empty (SCTE)
Enables the following interrupts:
–
–
–
–
Receiver overrun interrupts
Noise error interrupts
Framing error interrupts
Parity error interrupts
Address:
$003A
Bit 7
R8
R
6
5
0
4
0
3
2
NEIE
0
1
FEIE
0
Bit 0
PEIE
0
Read:
Write:
Reset:
T8
ORIE
R
0
R
0
U
U
0
R
= Reserved
U = Unaffected
Figure 13-10. SCI Control Register 3 (SCC3)
R8 — Received Bit 8
When the SCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8)
of the received character. R8 is received at the same time that the SCDR
receives the other eight bits.
When the SCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7).
Reset has no effect on the R8 bit.
T8 — Transmitted Bit 8
When the SCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8)
of the transmitted character. T8 is loaded into the transmit shift register at the
same time that the SCDR is loaded into the transmit shift register. Reset has no
effect on the T8 bit.
ORIE — Receiver Overrun Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests generated by the
receiver overrun bit, OR.
1 = SCI error CPU interrupt requests from OR bit enabled
0 = SCI error CPU interrupt requests from OR bit disabled
NEIE — Receiver Noise Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests generated by the
noise error bit, NE. Reset clears NEIE.
1 = SCI error CPU interrupt requests from NE bit enabled
0 = SCI error CPU interrupt requests from NE bit disabled
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA Serial Communications Interface Module (SCI)
Data Sheet
187
FREESCALE [ Freescale ]
