Low-Voltage Inhibit (LVI)
LVI Status and Control Register
9.3.4 LVI Trip Selection
The TRPSEL bit allows the user to chose between 5 percent and 10 percent
tolerance when monitoring the supply voltage. The 10 percent option is enabled
out of reset. Writing a 1 to TRPSEL will enable 5 percent option.
NOTE:
The microcontroller is guaranteed to operate at a minimum supply voltage. The trip
point (VLVR1 or VLVR2) may be lower than this. See 19.5 DC Electrical
Characteristics.
9.4 LVI Status and Control Register
The LVI status register (LVISCR) flags VDD voltages below the VLVRX level.
Address:
$FE0F
Bit 7
Read: LVIOUT
6
5
TRPSEL
0
4
0
3
0
2
0
1
0
Bit 0
0
0
Write:
R
0
R
R
0
R
0
R
0
R
0
R
Reset:
0
0
= Reserved
R
Figure 9-3. LVI Status and Control Register (LVISCR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the VDD voltage falls below the VLVRX
voltage for 32 to 40 CGMXCLK cycles. See Table 9-1. Reset clears the LVIOUT
bit.
Table 9-1. LVIOUT Bit Indication
VDD
LVIOUT
At Level:
For Number of CGMXCLK Cycles:
Any
VDD > VLVRX + VLVHX
0
V
V
V
DD < VLVRX
DD < VLVRX
DD < VLVRX
< 32 CGMXCLK cycles
Between 32 & 40 CGMXCLK cycles
> 40 CGMXCLK cycles
Any
0
0 or 1
1
V
LVRX < VDD < VLVRX + VLVHX
Previous value
TRPSEL — LVI Trip Select Bit
This bit selects the LVI trip point. Reset clears this bit.
1 = 5 percent tolerance. The trip point and recovery point are determined by
LVR1 and VLVH1, respectively.
0 = 10 percent tolerance. The trip point and recovery point are determined by
LVR2 and VLVH2, respectively.
V
V
NOTE:
If LVIRST and LVIPWR are 0s, note that when changing the tolerance, LVI reset
will be generated if the supply voltage is below the trip point.
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA
Data Sheet
109
Low-Voltage Inhibit (LVI)
FREESCALE [ Freescale ]
