Input/Output (I/O) Ports (PORTS)
Addr.
Register Name
Bit 7
DDRA7
0
6
5
4
3
2
1
Bit 0
DDRA0
0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Data Direction Register A
(DDRA)
See page 113.
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
$0004
0
DDRB6
0
0
DDRB5
0
0
DDRB4
0
0
DDRB3
0
0
DDRB2
0
0
DDRB1
0
Data Direction Register B
(DDRB)
See page 115.
DDRB7
DDRB0
0
$0005
0
0
Data Direction Register C
(DDRC)
See page 117.
DDRC6
0
DDRC5
0
DDRC4
0
DDRC3
0
DDRC2
0
DDRC1
0
DDRC0
0
$0006
$0007
R
0
Unimplemented
Read:
Write:
Reset:
Read:
Write:
Reset:
Port E Data Register
(PTE)
See page 120.
PTE7
PTE6
PTE5
PTF5
PTE4
PTE3
PTE2
PTF2
PTE1
PTF1
PTE0
PTF0
$0008
$0009
Unaffected by reset
PTF4 PTF3
Unaffected by reset
0
0
Port F Data Register
(PTF)
See page 122.
R
R
$000A
$000B
Unimplemented
Unimplemented
Read:
Write:
Reset:
Read:
Write:
Reset:
Data Direction Register E
(DDRE)
See page 120.
DDRE7
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
DDRE1
DDRE0
$000C
$000D
0
0
0
0
0
DDRF5
0
0
DDRF4
0
0
DDRF3
0
0
DDRF2
0
0
DDRF1
0
0
DDRF0
0
Data Direction Register F
(DDRF)
See page 122.
R
R
R
= Reserved
Figure 10-1. I/O Port Register Summary (Continued)
Data Sheet
112
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
Input/Output (I/O) Ports (PORTS) MOTOROLA
FREESCALE [ Freescale ]
