External Interrupt (IRQ)
IRQ Status and Control Register
If the MODE1 bit is clear, the IRQ pin is falling-edge-sensitive only. With MODE1
clear, a vector fetch or software clear immediately clears the IRQ1 latch.
Use the branch if IRQ pin high (BIH) or branch if IRQ pin low (BIL) instruction to
read the logic level on the IRQ pin.
NOTE:
When using the level-sensitive interrupt trigger, avoid false interrupts by masking
interrupt requests in the interrupt routine.
8.6 IRQ Status and Control Register
The IRQ status and control register (ISCR) has these functions:
•
•
•
Clears the IRQ interrupt latch
Masks IRQ interrupt requests
Controls triggering sensitivity of the IRQ interrupt pin
Address:
$003F
Bit 7
0
6
5
0
4
0
3
IRQF
0
2
0
1
IMASK1
0
Bit 0
MODE1
0
Read:
Write:
Reset:
0
R
R
R
0
R
0
ACK1
0
0
0
R
= Reserved
Figure 8-4. IRQ Status and Control Register (ISCR)
ACK1 — IRQ Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ latch. ACK1 always reads
as logic 0. Reset clears ACK1.
IMASK1 — IRQ Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ interrupt requests. Reset
clears IMASK1.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
MODE1 — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears
MODE1.
1 = IRQ interrupt requests on falling edges and low levels
0 = IRQ interrupt requests on falling edges only
IRQF — IRQ Flag
This read-only bit acts as a status flag, indicating an IRQ event occurred.
1 = External IRQ event occurred.
0 = External IRQ event did not occur.
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA External Interrupt (IRQ)
Data Sheet
105
FREESCALE [ Freescale ]
