Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
System initialization
3.5 System initialization
Registers and bits that control initialization and the basic operation of the
MCU are protected against writes except under special circumstances.
The following table lists registers that can be written only once after
reset, or that must be written within the first 64 cycles after reset.
Table 3-3. Registers with limited write access
Register
address
Register
name
Must be written in
first 64 cycles
(1)
Write
once only
$x024
$x035
$x037
$x038
$x039
$x03D
Timer interrupt mask register 2 (TMSK2)
Block protect register (BPROT)
—
—
(2)
EEPROM mapping register (INIT2)
No
Yes
(3)
System configuration options register 2 (OPT2)
System configuration options register (OPTION)
RAM and I/O map register (INIT)
No
(4)
—
—
Yes
1. Bits 1 and 0 can be written once and only in first 64 cycles; when SMOD = 1, however, these bits can be written at any
time. All other bits can be written at any time.
2. Bits can be written to zero once and only in first 64 cycles or in special modes. Bits can be set to one at any time.
3. Bit 4 (IRVNE) can be written only once.
4. Bits 5, 4, 2, 1, and 0 can be written once and only in first 64 cycles; when SMOD = 1, however, bits 5, 4, 2, 1, and 0 can
be written at any time. All other bits can be written at any time.
3.5.1 Mode selection
The four mode variations are selected by the logic states of the mode A
(MODA) and mode B (MODB) pins during reset. The MODA and MODB
logic levels determine the logic state of special mode (SMOD) and the
mode A (MDA) control bits in the highest priority I-bit interrupt and
miscellaneous (HPRIO) register.
After reset is released, the mode select pins no longer influence the
MCU operating mode. In single chip operating mode, MODA pin is
connected to a logic zero. In expanded mode, MODA is normally
connected to VDD through a pull-up resistor of 4.7 k¾. The MODA pin
also functions as the load instruction register (LIR) pin when the MCU is
not in reset. The open-drain active low LIR output pin drives low during
the first E cycle of each instruction. The MODB pin also functions as the
MC68HC11P2 — Rev 1.0
Technical Data
Operating Modes and On-Chip Memory
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