Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
System initialization
Table 3-4. Hardware mode select summary
Control bits in HPRIO
(latched at reset)
Inputs
Mode
MODB
MODA
RBOOT SMOD
MDA
1
1
0
0
0
1
0
1
Single chip
Expanded
0
0
1
0
0
0
1
1
0
1
0
1
Special bootstrap
Special test
PSEL[4:0] — Priority select bits (refer to Resets and Interrupts)
3.5.2 Initialization
Because bits in the following registers control the basic configuration of
the MCU, an accidental change of their values could cause serious
system problems. The protection mechanism, overridden in special
operating modes, requires a write to the protected bits only within the
first 64 bus cycles after any reset, or only once after each reset. See
Table 3-3.
3.5.2.1 CONFIG — System configuration register
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
ROMA
D
PARE NOSE NOCO ROMO
Configuration control (CONFIG) $003F
1
1
EEON x11x 1xxx
N
C
P
N
CONFIG controls the presence and/or location of ROM and EEPROM in
the memory map and enables the COP watchdog system. A security
feature that protects data in EEPROM and RAM is available on mask
programmed MCUs, controlled by the NOSEC bit. Refer to RAM and
EEPROM security.
CONFIG is made up of EEPROM cells and static working latches. The
operation of the MCU is controlled directly by these latches and not the
EEPROM byte. When programming the CONFIG register, the EEPROM
MC68HC11P2 — Rev 1.0
Technical Data
Operating Modes and On-Chip Memory
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