Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
Table 3-2. Register and control bit assignments (Sheet 2 of 4)
State
on reset
Register name
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Timer output compare 4 (TOC4) high $001C (bit 15) (14)
Timer output compare 4 (TOC4) low $001D (bit 7) (6)
Capture 4/compare 5 (TI4/O5) high $001E (bit 15) (14)
(13)
(5)
(12)
(4)
(11)
(3)
(10)
(2)
(9)
(1)
(bit 8) 1111 1111
(bit 0) 1111 1111
(bit 8) 1111 1111
(bit 0) 1111 1111
OL5 0000 0000
(13)
(5)
(12)
(4)
(11)
(3)
(10)
(2)
(9)
Capture 4/compare 5 (TI4/O5) low $001F (bit 7)
(6)
(1)
Timer control 1 (TCTL1)
Timer control 2 (TCTL2)
$0020
OM2
OL2
OM3
OL3
OM4
OL4
OM5
$0021 EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A 0000 0000
Timer interrupt mask 1 (TMSK1)
Timer interrupt flag 1 (TFLG1)
Timer interrupt mask 2 (TMSK2)
Timer interrupt flag 2 (TFLG2)
$0022 OC1I OC2I OC3I OC4I I4/O5I IC1I
$0023 OC1F OC2F OC3F OC4F I4/O5F IC1F
IC2I
IC2F
PR1
0
IC3I 0000 0000
IC3F 0000 0000
PR0 0000 0000
$0024
$0025
TOI
TOF
0
RTII PAOVI PAII
RTIF PAOVF PAIF
PAEN PAMOD PEDGE
0
0
0
0
0
0000 0000
Pulse accumulator control (PACTL) $0026
0
I4/O5 RTR1 RTR0 0000 0000
(2) (1) (bit 0) undefined
Pulse accumulator count (PACNT)
SPI control (SPCR)
$0027 (bit 7)
(6)
(5)
(4)
(3)
$0028
$0029
SPIE
SPE DWOM MSTR CPOL CPHA SPR1 SPR0 0000 01uu
SPI status (SPSR)
SPIF WCOL
0
MODF
(4)
0
0
(2)
0
0
(1)
0
0
0000 0000
SPI data (SPDR)
$002A (bit 7)
(6)
0
(5)
(3)
(bit 0) undefined
EPGM 0000 0000
EPROM programming (EPROG) ‡
Port pull-up assignment (PPAR)
reserved
$002B
$002C
$002D
MBE
0
ELAT EXCOL EXROW
0
0
0
HPPUE GPPUE FPPUE BPPUE 0000 1111
PLL control (PLLCR)
$002E PLLON BCS AUTO BWC VCOT MCS
LCK
WEN 1010 1000
Synthesizer program (SYNR)
A/D control & status (ADCTL)
A/D result 1 (ADR1)
$002F SYNX1 SYNX0 SYNY5 SYNY4 SYNY3 SYNY2 SYNY1 SYNY0 0000 1011
$0030
CCF
0
SCAN MULT
CD
(3)
(3)
(3)
(3)
CC
(2)
(2)
(2)
(2)
CB
(1)
(1)
(1)
(1)
CA
u0uu uuuu
$0031 (bit 7)
$0032 (bit 7)
$0033 (bit 7)
$0034 (bit 7)
$0035 BULKP
$0036
(6)
(6)
(6)
(6)
0
(5)
(5)
(5)
(5)
(4)
(4)
(4)
(4)
(bit 0) undefined
(bit 0) undefined
(bit 0) undefined
(bit 0) undefined
A/D result 2 (ADR2)
A/D result 3 (ADR3)
A/D result 4 (ADR4)
Block protect (BPROT)
reserved
BPRT4 PTCON BPRT3 BPRT2 BPRT1 BPRT0 1011 1111
EEPROM mapping (INIT2)
System config. options 2 (OPT2)
$0037
EE3
EE2
EE1
EE0 M3DL1 M3DL0 M2DL1 M2DL0 0000 0000
$0038 LIRDV CWOM STRCH IRVNE LSBF SPR2
0
0
000x 0000
System config. options 1 (OPTION) $0039 ADPU CSEL IRQE
DLY
(4)
CME FCME CR1
CR0 0001 0000
(bit 0) undefined
COP timer arm/reset (COPRST)
EEPROM programming (PPROG)
Highest priority interrupt (HPRIO)
RAM & I/O mapping (INIT)
$003A (bit 7)
(6)
(5)
0
(3)
(2)
(1)
$003B ODD EVEN
BYTE ROW ERASE EELAT EEPGM 0000 0000
$003C RBOOT SMOD MDA PSEL4 PSEL3 PSEL2 PSEL1 PSEL0 xxx0 0110
$003D RAM3 RAM2 RAM1 RAM0 REG3 REG2 REG1 REG0 0000 0000
Technical Data
MC68HC11P2 — Rev 1.0
Operating Modes and On-Chip Memory
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