Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
On-chip memory
3.4.2 Registers
In Table 3-2, a summary of registers and control bits, the registers are
shown in ascending order within the 128-byte register block. The
addresses shown are for default block mapping ($0000–$007F),
however, the INIT register remaps the block to any 4k page
($x000–$x07F).
Table 3-2. Register and control bit assignments (Sheet 1 of 4)
State
on reset
Register name
Address bit 7
$0000 PA7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Port A data (PORTA)
Data direction A (DDRA)
PA6
PA5
PA4
PA3
PA2
PA1
PA0 undefined
$0001 DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 0000 0000
$0002 DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 0000 0000
$0003 DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 0000 0000
Data direction B (DDRB)
Data direction F (DDRF)
Port B data (PORTB)
$0004
$0005
$0006
PB7
PF7
PC7
PB6
PF6
PC6
PB5
PF5
PC5
PB4
PF4
PC4
PB3
PF3
PC3
PB2
PF2
PC2
PB1
PF1
PC1
PB0 undefined
PF0 undefined
PC0 undefined
Port F data (PORTF)
Port C data (PORTC)
Data direction C (DDRC)
Port D data (PORTD)
$0007 DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 0000 0000
$0008
$0009
$000A
0
0
0
0
PD5
PD4
PD3
PD2
PD1
PD0 undefined
Data direction D (DDRD)
Port E data (PORTE)
DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 0000 0000
PE7
PE6
PE5
PE4
PE3
PE2
0
PE1
0
PE0 undefined
Timer compare force (CFORC)
Output compare 1 mask (OC1M)
Output compare 1 data (OC1D)
Timer count (TCNT) high
Timer count (TCNT) low
$000B FOC1 FOC2 FOC3 FOC4 FOC5
$000C OC1M7 OC1M6 OC1M5 OC1M4 OC1M3
$000D OC1D7 OC1D6 OC1D5 OC1D4 OC1D3
0
0
0
0000 0000
0000 0000
0000 0000
0
0
0
0
$000E (bit 15) (14)
$000F (bit 7) (6)
$0010 (bit 15) (14)
$0011 (bit 7) (6)
$0012 (bit 15) (14)
$0013 (bit 7) (6)
$0014 (bit 15) (14)
$0015 (bit 7) (6)
(13)
(5)
(12)
(4)
(11)
(3)
(10)
(2)
(9)
(1)
(9)
(1)
(9)
(1)
(9)
(1)
(9)
(1)
(9)
(1)
(bit 8) 0000 0000
(bit 0) 0000 0000
(bit 8) undefined
(bit 0) undefined
(bit 8) undefined
(bit 0) undefined
(bit 8) undefined
(bit 0) undefined
(bit 8) 1111 1111
(bit 0) 1111 1111
(bit 8) 1111 1111
(bit 0) 1111 1111
Timer input capture 1 (TIC1) high
Timer input capture 1 (TIC1) low
Timer input capture 2 (TIC2) high
Timer input capture 2 (TIC2) low
Timer input capture 3 (TIC3) high
Timer input capture 3 (TIC3) low
(13)
(5)
(12)
(4)
(11)
(3)
(10)
(2)
(13)
(5)
(12)
(4)
(11)
(3)
(10)
(2)
(13)
(5)
(12)
(4)
(11)
(3)
(10)
(2)
Timer output compare 1 (TOC1) high $0016 (bit 15) (14)
Timer output compare 1 (TOC1) low $0017 (bit 7) (6)
Timer output compare 2 (TOC2) high $0018 (bit 15) (14)
Timer output compare 2 (TOC2) low $0019 (bit 7) (6)
(13)
(5)
(12)
(4)
(11)
(3)
(10)
(2)
(13)
(5)
(12)
(4)
(11)
(3)
(10)
(2)
MC68HC11P2 — Rev 1.0
Technical Data
Operating Modes and On-Chip Memory
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