Freescale Semiconductor, Inc.
Resets and Interrupts
10.4 Effects of reset
When a reset condition is recognized, the internal registers and control
bits are forced to an initial state. Depending on the cause of the reset and
the operating mode, the reset vector can be fetched from any of six
possible locations, as shown in Table 10-2.
Table 10-2. Reset cause, reset vector and operating mode
Cause of reset
POR or RESET pin
Clock monitor failure
COP watchdog timeout
Normal mode vector Special test or bootstrap
$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
$BFFE, $BFFF
$BFFC, $BFFD
$BFFA, $BFFB
These initial states then control on-chip peripheral systems to force them
to known start-up states, as described in the following paragraphs.
10.4.1 Central processing unit
After reset, the CPU fetches the restart vector from the appropriate
address during the first three cycles, and begins executing instructions.
The stack pointer and other CPU registers are indeterminate
immediately after reset; however, the X and I interrupt mask bits in the
condition code register (CCR) are set to mask any interrupt requests.
Also, the S-bit in the CCR is set to inhibit the STOP mode.
10.4.2 Memory map
After reset, the INIT register is initialized to $00, putting the 1024 bytes
of RAM at locations $0080 –$047F, and the control registers at locations
$0000–$007F. The INIT2 register puts EEPROM at locations
$0D80–$0FFF.
Technical Data
MC68HC11P2 — Rev 1.0
Resets and Interrupts
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