Freescale Semiconductor, Inc.
Resets and Interrupts
these two steps is possible as long as both steps are completed in the
correct sequence before the timer times out.
10.3.5 Clock monitor reset
The clock monitor circuit is based on an internal RC time delay. If no
MCU clock edges are detected within this RC time delay, the clock
monitor can optionally generate a system reset. The clock monitor
function is enabled or disabled by the CME control bit in the OPTION
register. The presence of a timeout is determined by the RC delay, which
allows the clock monitor to operate without any MCU clocks.
Clock monitor is used as a backup for the COP system. Because the
COP needs a clock to function, it is disabled when the clocks stop.
Therefore, the clock monitor system can detect clock failures not
detected by the COP system.
Semiconductor wafer processing causes variations of the RC timeout
values between individual devices. An E clock frequency below 10 kHz
is detected as a clock monitor error. An E clock frequency of 200 kHz or
more prevents clock monitor errors. Using the clock monitor function
when the E clock is below 200 kHz is not recommended.
Special considerations are needed when a STOP instruction is executed
and the clock monitor is enabled. Because the STOP function causes
the clocks to be halted, the clock monitor function generates a reset
sequence if it is enabled at the time the STOP mode was initiated. Before
executing a STOP instruction, clear the CME bit in the OPTION register
to zero to disable the clock monitor. After recovery from STOP, set the
CME bit to logic one to enable the clock monitor.
Technical Data
MC68HC11P2 — Rev 1.0
Resets and Interrupts
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