Freescale Semiconductor, Inc.
Resets and Interrupts
Effects of reset
10.4.3 Parallel I/O
When a reset occurs in expanded operating modes, port B, C, and F pins
used for parallel I/O are dedicated to the expansion bus. If a reset occurs
during a single chip operating mode, all ports are configured as general-
purpose high-impedance inputs.
NOTE: Do not confuse pin function with the electrical state of the pin at reset. All
general-purpose I/O pins configured as inputs at reset are in a high-
impedance state. Port data registers reflect the port’s functional state at
reset. The pin function is mode dependent.
10.4.4 Timer
During reset, the timer system is initialized to a count of $0000. The
prescaler bits are cleared, and all output compare registers are initialized
to $FFFF. All input capture registers are indeterminate after reset. The
output compare 1 mask (OC1M) register is cleared so that successful
OC1 compares do not affect any I/O pins. The other four output
compares are configured so that they do not affect any I/O pins on
successful compares. All input capture edge-detector circuits are
configured for capture disabled operation. The timer overflow interrupt
flag and all eight timer function interrupt flags are cleared. All nine timer
interrupts are disabled because their mask bits have been cleared.
The I4/O5 bit in the PACTL register is cleared to configure the I4/O5
function as OC5; however, the OM5:OL5 control bits in the TCTL1
register are clear so OC5 does not control the PA3 pin.
10.4.5 Real-time interrupt (RTI)
The real-time interrupt flag (RTIF) is cleared and automatic hardware
interrupts are masked. The rate control bits are cleared after reset and
can be initialized by software before the real-time interrupt (RTI) system
is used.
MC68HC11P2 — Rev 1.0
Technical Data
Resets and Interrupts
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