Freescale Semiconductor, Inc.
Resets and Interrupts
This control bit can be read or written at any time and controls whether
or not the internal clock monitor circuit triggers a reset sequence when
the system clock is slow or absent. When it is clear, the clock monitor
circuit is disabled, and when it is set, the clock monitor circuit is
enabled. Reset clears the CME bit.
In order to use both STOP and clock monitor, the CME bit should be
cleared before executing STOP, then set again after recovering from
STOP.
FCME — Force clock monitor enable
1 = Clock monitor enabled; cannot be disabled until next reset.
0 = Clock monitor follows the state of the CME bit.
When FCME is set, slow or stopped clocks will cause a clock failure
reset sequence. To utilize STOP mode, FCME should always be
cleared.
CR[1:0] — COP timer rate select bits
The internal E clock is first divided by 215 before it enters the COP
watchdog system. These control bits determine a scaling factor for the
watchdog timer. See Table 10-1.
10.3.7 CONFIG — Configuration control register
State
on reset
Address bit 7
bit 6
1
bit 5 bit 4
bit 3
bit 2 bit 1
bit 0
Configuration control (CONFIG) $003F ROMAD
1
PARENNOSECNOCOPROMON EEON x11x xxxx
CONFIG controls the presence and location of EEPROM in the memory
map and enables the COP watchdog system. A security feature that
protects data in EEPROM and RAM is available on mask programmed
MCUs. Refer to RAM and EEPROM security.
CONFIG is made up of EEPROM cells and static working latches. The
operation of the MCU is controlled directly by these latches and not the
EEPROM byte. When programming the CONFIG register, the EEPROM
byte is accessed. When the CONFIG register is read, the static latches
Technical Data
MC68HC11P2 — Rev 1.0
Resets and Interrupts
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