Freescale Semiconductor, Inc.
Resets and Interrupts
Reset and interrupt priority
10.4.10 Analog-to-digital converter
The A/D converter configuration is indeterminate after reset. The ADPU
bit is cleared by reset, which disables the A/D system. The conversion
complete flag is cleared by reset.
10.4.11 System
The EEPROM programming controls are disabled, so the memory
system is configured for normal read operation. PSEL[4:0] are initialized
with the binary value %00110, causing the external IRQ pin to have the
highest I-bit interrupt priority. The IRQ pin is configured for level-
sensitive operation (for wired-OR systems). The RBOOT, SMOD, and
MDA bits in the HPRIO register reflect the status of the MODB and
MODA inputs at the rising edge of reset. The DLY control bit is set to
specify that an oscillator start-up delay is imposed upon recovery from
STOP mode. The clock monitor system is disabled because CME and
FCME are cleared.
10.5 Reset and interrupt priority
Resets and interrupts have a hardware priority that determines which
reset or interrupt is serviced first when simultaneous requests occur. Any
maskable interrupt can be given priority over other maskable interrupts.
The first six interrupt sources are not maskable by the I-bit in the CCR.
The priority arrangement for these sources is fixed and is as follows:
1. POR or RESET pin
2. Clock monitor reset
3. COP watchdog reset
4. XIRQ interrupt
– Illegal opcode interrupt — see Illegal opcode trap for details
of handling
MC68HC11P2 — Rev 1.0
Technical Data
Resets and Interrupts
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