Freescale Semiconductor, Inc.
Resets and Interrupts
The maskable interrupt sources have the following priority arrangement:
1. IRQ
2. Real-time interrupt
3. Timer input capture 1
4. Timer input capture 2
5. Timer input capture 3
6. Timer output compare 1
7. Timer output compare 2
8. Timer output compare 3
9. Timer output compare 4
10. Timer input capture 4/output compare 5
11. SCI2/MI BUS system
12. SCI3/MI BUS system
13. Timer overflow
14. Pulse accumulator overflow
15. Pulse accumulator input edge
16. SPI transfer complete
17. SCI1 system
Any one of these maskable interrupts can be assigned the highest
maskable interrupt priority by writing the appropriate value to the PSEL
bits in the HPRIO register. Otherwise, the priority arrangement remains
the same. An interrupt that is assigned highest priority is still subject to
global masking by the I-bit in the CCR, or by any associated local bits.
Interrupt vectors are not affected by priority assignment. To avoid race
conditions, HPRIO can only be written while I-bit interrupts are inhibited.
Technical Data
MC68HC11P2 — Rev 1.0
Resets and Interrupts
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