Freescale Semiconductor, Inc.
Resets and Interrupts
10.4.6 Pulse accumulator
The pulse accumulator system is disabled at reset so that the pulse
accumulator input (PAI) pin defaults to being a general-purpose input
pin.
10.4.7 Computer operating properly (COP)
The COP watchdog system is enabled if the NOCOP control bit in the
CONFIG register is cleared, and disabled if NOCOP is set. The COP rate
is set for the shortest duration timeout.
10.4.8 Serial communications interface (SCI)
The reset condition of the SCI system is independent of the operating
mode. At reset, the SCI baud rate control register is initialized to $0004.
All transmit and receive interrupts are masked and both the transmitter
and receiver are disabled so the port pins default to being general
purpose I/O lines. The SCI frame format is initialized to an 8-bit character
size. The send break and receiver wake-up functions are disabled. The
TDRE and TC status bits in the SCI status register are both set,
indicating that there is no transmit data in either the transmit data register
or the transmit serial shift register. The RDRF, IDLE, OR, NF, FE, PF,
and RAF receive-related status bits are cleared.
NOTE: The foregoing paragraph also applies to SCI2 and SCI3. Their
respective MI BUS functions are disabled, since MIEx is cleared on
reset.
10.4.9 Serial peripheral interface (SPI)
The SPI system is disabled by reset. The port pins associated with this
function default to being general-purpose I/O lines.
Technical Data
MC68HC11P2 — Rev 1.0
Resets and Interrupts
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