Freescale Semiconductor, Inc.
Resets and Interrupts
10.3.1 Power-on reset
A positive transition on VDD generates a power-on reset (POR), which
is used only for power-up conditions. POR cannot be used to detect
drops in power supply voltages. A 4064 tCYC (internal clock cycle) delay
after the oscillator becomes active allows the clock generator to
stabilize. If RESET is at logical zero at the end of 4064 tCYC, the CPU
remains in the reset condition until RESET goes to logical one.
It is important to protect the MCU during power transitions. Most
M68HC11 systems need an external circuit that holds the RESET pin
low whenever VDD is below the minimum operating level. This external
voltage level detector, or other external reset circuits, are the usual
source of reset in a system. The POR circuit only initializes internal
circuitry during cold starts. Refer to Figure 2-2.
10.3.2 External reset (RESET)
The CPU distinguishes between internal and external reset conditions
by sensing whether the reset pin rises to a logic one in less than two E
clock cycles after an internal device releases reset. When a reset
condition is sensed, the RESET pin is driven low by an internal device
for four E clock cycles, then released. Two E clock cycles later it is
sampled. If the pin is still held low, the CPU assumes that an external
reset has occurred. If the pin is high, it indicates that the reset was
initiated internally by either the COP system or the clock monitor. It is not
advisable to connect an external resistor capacitor (RC) power-up delay
circuit to the reset pin of M68HC11 devices because the circuit charge
time constant can cause the device to misinterpret the type of reset that
occurred.
10.3.3 COP reset
The MCU includes a COP system to help protect against software
failures. When the COP is enabled, the software is responsible for
keeping a free-running watchdog timer from timing out. When the
Technical Data
MC68HC11P2 — Rev 1.0
Resets and Interrupts
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