Freescale Semiconductor, Inc.
Analog-to-Digital Converter
9.7 Operation in STOP and WAIT modes
If a conversion sequence is in progress when either the STOP or WAIT
mode is entered, the conversion of the current channel is suspended.
When the MCU resumes normal operation, that channel is resampled
and the conversion sequence is resumed. As the MCU exits the WAIT
mode, the A/D circuits are stable and valid results can be obtained on
the first conversion. However, in STOP mode, all analog bias currents
are disabled and it is necessary to allow a stabilization period when
leaving the STOP mode. If the STOP mode is exited with a delay
(DLY = 1), there is enough time for these circuits to stabilize before the
first conversion. If the STOP mode is exited with no delay (DLY bit in
OPTION register = 0), allow 10 ms for the A/D circuitry to stabilize to
avoid invalid results.
Technical Data
MC68HC11P2 — Rev 1.0
Analog-to-Digital Converter
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