Freescale Semiconductor, Inc.
Timing System
CON12 — Concatenate Channels 1 and 2
1 = Channels 1 and 2 are concatenated into one 16-bit PWM
channel.
0 = Channels 1 and 2 are separate 8-bit PWMs.
When concatenated, channel 1 is the high-order byte and the channel
2 pin (PH1) is the output.
8.9.2.2 Clock prescaler selection
The three available clocks are clock A, clock B, and clock S (scaled).
Clock A can be software selected to be E, E/2, E/4, or E/8. Clock B can
be software selected to be E, E/2, E/4,..., E/128. The scaled clock (clock
S) uses clock A as an input and divides it with a reloadable counter. The
rates available are software selectable to be clock A/2, down to clock A
/512.
The clock source portion of the block diagram shows the three clock
sources and how the scaled clock is created. Clock A is an input to an 8-
bit counter which is then compared to a user programmable scale value.
When they match, this circuit has an output that is divided by two and the
counter is reset.
Each PWM timer channel can be driven by one of two clocks. Refer to
Figure 8-4.
PCKA[2:1] — Prescaler for clock A
Determines the frequency of clock A. Refer to Table 8-4.
Bit 3 — Not implemented; always reads zero
PCKB[3:1] — Prescaler for clock B
Determines the frequency of clock B. Refer to Table 8-4.
Technical Data
MC68HC11P2 — Rev 1.0
Timing System
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