Freescale Semiconductor, Inc.
Timing System
8.9.8 PWDTY1–4 — PWM timer duty cycle registers 1 to 4
State
on reset
Address bit 7
bit 6
bit 5 bit 4
bit 3
bit 2
bit 1
bit 0
Pulse width duty 1 (PWDTY1) $006C (bit 7)
Pulse width duty 2 (PWDTY2) $006D (bit 7)
Pulse width duty 3 (PWDTY3) $006E (bit 7)
Pulse width duty 4 (PWDTY4) $006F (bit 7)
(6)
(6)
(6)
(6)
(5)
(5)
(5)
(5)
(4)
(4)
(4)
(4)
(3)
(3)
(3)
(3)
(2)
(2)
(2)
(2)
(1) (bit 0) 1111 1111
(1) (bit 0) 1111 1111
(1) (bit 0) 1111 1111
(1) (bit 0) 1111 1111
There is one duty register for each channel. The value in this register
determines the duty cycle of the associated PWM timer channel.
PWDTYx is compared to the counter contents and if they are equal, a
match occurs and the output goes to the state defined by the associated
polarity bit. If the register is written while the channel is enabled, then the
new value is held in a buffer until the counter rolls over or the channel is
disabled. Reads of this register return the most recent value written.
NOTE: If PWDTYx Š PWPERx then there will be no change of state due to the
duty cycle value. In addition, if the duty register is set to $00, then the
output will always be in the state which would normally be result from the
duty change of state (see also Boundary cases).
PWMx
PWDTYx
PWPERx
Figure 8-5. PWM duty cycle
Technical Data
MC68HC11P2 — Rev 1.0
Timing System
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