Freescale Semiconductor, Inc.
Timing System
are inhibited, and the system operates in a polled mode, which
requires that PAOVF be polled by user software to determine when
an overflow has occurred. When the PAOVI control bit is set, a
hardware interrupt request is generated each time PAOVF is set.
Before leaving the interrupt service routine, software must clear
PAOVF by writing to the TFLG2 register.
PAII and PAIF — Pulse accumulator input edge interrupt enable and flag
The PAIF status bit is automatically set each time a selected edge is
detected at the PA7/PAI/OC1 pin. To clear this status bit, write to the
TFLG2 register with a one in the corresponding data bit position (bit
4). The PAII control bit allows configuring the pulse accumulator input
edge detect for polled or interrupt-driven operation but does not affect
setting or clearing the PAIF bit. When PAII is zero, pulse accumulator
input interrupts are inhibited, and the system operates in a polled
mode. In this mode, the PAIF bit must be polled by user software to
determine when an edge has occurred. When the PAII control bit is
set, a hardware interrupt request is generated each time PAIF is set.
Before leaving the interrupt service routine, software must clear PAIF
by writing to the TFLG register.
8.9 Pulse-width modulation (PWM) timer
The PWM timer subsystem provides up to four 8-bit pulse-width
modulated waveforms on the port H pins. Channel pairs can be
concatenated to create 16-bit PWM outputs. Three clock sources (A, B,
and S) and a flexible clock select scheme give the PWM a wide range of
frequencies.
Alternate
function
Pin
PH0
PH1
PH2
PH3
PW1
PW2
PW3
PW4
Technical Data
MC68HC11P2 — Rev 1.0
Timing System
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