Freescale Semiconductor, Inc.
Timing System
8.8.1 PACTL — Pulse accumulator control register
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Pulse accumulator control
(PACTL)
$0026
0
PAEN PAMODPEDGE
0
I4/O5 RTR1 RTR0 0000 0000
Four of this register’s bits control an 8-bit pulse accumulator system.
Another bit enables either the OC5 function or the IC4 function, while two
other bits select the rate for the real-time interrupt system.
Bits [7, 3] — Not implemented; always read zero
PAEN — Pulse accumulator system enable
1 = Pulse accumulator enabled.
0 = Pulse accumulator disabled.
PAMOD — Pulse accumulator mode
1 = Gated time accumulation mode.
0 = Event counter mode.
PEDGE — Pulse accumulator edge control
This bit has different meanings depending on the state of the PAMOD
bit, as shown:
PAMOD PEDGE
Action of clock
0
0
1
1
0
1
0
1
PAI falling edge increments the counter.
PAI rising edge increments the counter.
A zero on PAI inhibits counting.
A one on PAI inhibits counting.
I4/O5 — Input capture 4/output compare 5
1 = Input capture 4 function is enabled (no OC5).
0 = Output compare 5 function is enabled (no IC4).
RTR[1:0] — RTI interrupt rate selects (refer to Real-time interrupt)
Technical Data
MC68HC11P2 — Rev 1.0
Timing System
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
