Freescale Semiconductor, Inc.
Timing System
8.8 Pulse accumulator
The MC68HC11P2 has an 8-bit counter that can be configured to
operate either as a simple event counter, or for gated time accumulation,
depending on the state of the PAMOD bit in the PACTL register. Refer
to the pulse accumulator block diagram, Figure 8-3.
In the event counting mode, the 8-bit counter is clocked to increasing
values by an external pin. The maximum clocking rate for the external
event counting mode is the E clock divided by two. In gated time
accumulation mode, a free-running E clock ÷ 64 signal drives the 8-bit
counter, but only while the external PAI pin is activated. Refer to Table
8-3. The pulse accumulator counter can be read or written at any time.
Table 8-3. Pulse accumulator timing
Crystal
frequency
Cycle
time
PACNT
overflow
E clock
64/E
4.0 MHz
8.0 MHz
12.0 MHz
16.0 MHz
1.0 MHz
2.0 MHz
3.0 MHz
4.0 MHz
1000 ns
500 ns
333 ns
250 ns
64 µs
32 µs
16.384 ms
8.192 ms
5.461 ms
4.096 ms
21.33 µs
16.0 µs
Technical Data
MC68HC11P2 — Rev 1.0
Timing System
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