Freescale Semiconductor, Inc.
Timing System
Pulse accumulator
8.8.2 PACNT — Pulse accumulator count register
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
$0027 (bit 7) (6) (5) (4) (3) (2)
Pulse accumulator count
(PACNT)
(1) (bit 0) undefined
This 8-bit read/write register contains the count of external input events
at the PAI input, or the accumulated count. In gated time accumulation
mode, PACNT is readable even if PAI is not active. The counter is not
affected by reset and can be read or written at any time. Counting is
synchronized to the internal PH2 clock so that incrementing and reading
occur during opposite half cycles.
8.8.3 Pulse accumulator status and interrupt bits
The pulse accumulator control bits, PAOVI and PAII, PAOVF, and PAIF
are located within timer registers TMSK2 and TFLG2.
8.8.3.1 TMSK2 — Timer interrupt mask 2 register
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Timer interrupt mask 2 (TMSK2) $0024 TOI RTII PAOVI PAII PR1 PR0 0000 0000
0
0
8.8.3.2 TFLG2 — Timer interrupt flag 2 register
State
on reset
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Timer interrupt flag 2 (TFLG2) $0025 TOF RTIF PAOVF PAIF
0
0
0
0
0000 0000
PAOVI and PAOVF — Pulse accumulator interrupt enable and overflow
flag
The PAOVF status bit is set each time the pulse accumulator count
rolls over from $FF to $00. To clear this status bit, write a one in the
corresponding data bit position (bit 5) of the TFLG2 register. The
PAOVI control bit allows configuring the pulse accumulator overflow
MC68HC11P2 — Rev 1.0
Technical Data
Timing System
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